The invention relates generally to forming thin films over textured bottom electrodes, and more particularly to providing high permittivity dielectric and top electrode materials with near perfect conformality over memory cell bottom electrodes including hemispherical grain (HSG) silicon.
When fabricating integrated circuits, layers of insulating, conducting and semiconducting materials are deposited and patterned, layer by layer, to build up the desired circuit. Many types of circuits incorporate capacitors, each of which include a dielectric layer sandwiched two plates or electrodes. Memory chips such as dynamic random access memories (DRAMs), in particular, employ capacitors to store charge in memory cells. Each memory cell can represent one bit of data, where the capacitor can either be charged or discharged to represent logical states.
In accordance with the general trend in the semiconductor industry, integrated circuits are continually being scaled down in pursuit of faster processing speeds and lower power consumption. As the packing density of memory chips continues to increase, each capacitor in the more crowded memory cell must still maintain a certain minimum charge storage to ensure reliable operation of the memory cell without excessive refresh cycling. It is thus important that, with progressive generations of circuit design, capacitor designs achieve ever higher stored charge for the shrinking area of the chip (or footprint) allotted to each cell. Techniques have therefore been developed to increase the total charge capacity of the cell capacitor for a given footprint allotment.
The amount of charge stored on the capacitor is proportional to the capacitance, C=kk0A/d, where k is the permittivity or dielectric constant of the capacitor dielectric between two electrodes; k0 is the vacuum permittivity; A is the electrode surface area; and d is the spacing between the electrodes, also representing the thickness of the inter-electrode dielectric. Early techniques have focused on increasing the effective surface area of the electrodes by creating folding structures for stacked capacitors or trench capacitors. Trench capacitors are formed within the semiconductor substrate in which the transistors are generally formed, whereas stacked capacitors are formed above the transistors. Such structures better utilize the available chip area by creating three-dimensional shapes to which the conductive electrodes and capacitor dielectric conform.
FIG. 1A illustrates a memory cell 10 incorporating an exemplary stacked capacitor above a semiconductor substrate 12. The illustrated capacitor design is known in the industry as a xe2x80x9cstudxe2x80x9d capacitor. Transistors are first formed, including gate stacks 14 formed over the substrate 12 and heavily doped active areas 16 within the substrate 12. A contact 18 reaches through an, insulating layer 20 that overlies the transistors. This contact 18 electrically connects a lower or storage electrode 22, of the capacitor 11, which is formed over the insulating layer 20. The stud shape presents a larger surface area for the lower electrode 22, relative to the footprint of the substrate over which it is formed. A thin capacitor dielectric layer 24 coats the lower or bottom electrode 22, and an upper or top electrode 26 is formed over the capacitor dielectric 24.
FIG. 1B, for example, illustrates a memory cell 10a with a different stacked capacitor design, where like parts are referred to by like reference numerals. As in FIG. 1B, a capacitor 11a is shown over a substrate 12, including transistors covered with an insulating layer 20. The capacitor 11a, however, conforms to a generally cylindrical shape. In particular, a lower or bottom electrode 22a, electrically connecting to an underlying transistor by the contact 18, conforms to a cylinder, presenting a larger surface area relative to the footprint of the substrate over which it is formed. With both inner and outer surfaces exposed, as shown, the bottom electrode 22a has an even larger effective surface area than the corresponding bottom electrode 22 of the stud capacitor 11 in FIG. 1A. A thin capacitor dielectric layer 24a coats the bottom electrode 22a, and a top electrode 26a is formed over the capacitor dielectric 24a. xe2x80x9cCrownxe2x80x9d structures are similar to the illustrated cylindrical capacitor 11a of FIG. 1B but further include multiple concentric cylinders. Other stacked capacitor designs resemble mushroom shapes, finned structures, pins and a variety of other complicated structures formed above a semiconductor substrate.
FIG. 2, in contrast to the stacked capacitors of FIGS. 1A and 1B, illustrates a memory cell 30 incorporating an exemplary trench capacitor 31, formed largely within a semiconductor substrate 32. As with the stacked capacitors of the previous figures, a transistor includes a gate stack 34 over the substrate 32 and heavily doped active areas 36 within the substrate 32. The drain region (one of the active areas 36) electrically contacts a lower or storage electrode 42 of the capacitor 31. Doping or otherwise making conductive the walls of a trench in the semiconductor substrate 32 forms this lower electrode 42. By conforming to the walls of the trench, a larger surface area is provided for the lower electrode 42, relative to the footprint of the substrate 32 in which it is formed. A thin capacitor dielectric layer 44 coats the bottom electrode 42, and a top or reference electrode 46 is formed over the capacitor dielectric 44.
Relying solely on such structures for increasing the capacitance of the memory cell, however, becomes impractical with advancing generations of memory chip circuit designs. The surface area of a stud capacitor can theoretically be increased infinitely simply by increasing the height of the bottom electrode. Similarly, the depth of trench capacitors can be increased almost to the thickness of the substrate within which it is formed. Unfortunately, limits are imposed upon the height or depth of features in integrated circuits. As is well known in the art, it can be difficult to conformally coat, line or fill features with high steps using conventional deposition techniques. Additionally, increased topography on a chip can adversely affect the resolution of later photolithographic processes.
Rather than relying solely upon the height or depth of the cell capacitor, therefore, a microstructure can be added to further increase the surface area of the capacitor electrodes, by providing a textured or roughened surface to the macrostructural folds of the lower electrode. For example, polycrystalline conductive materials can be roughened by preferentially etching along grain boundaries, as disclosed, for example, in U.S. Pat. No. 3,405,801, issued to Han et al. Alternatively, U.S. Pat. No. 5,372,962, issued to Hirota et al., describes various selective etch processes for perforating a polysilicon layer.
Another class of electrode texturing techniques involves formation of hemispherical grained (HSG) silicon. Several methods for forming HSG silicon are known, including direct deposition, whereby deposited polysilicon selectively grows over nucleation sites, and redistribution anneal of amorphous silicon, whereby thermal energy causes silicon atoms to migrate about a surface and conglomerate about nucleation sites. FIGS. 1A and 1B show the lower electrodes 22, 22a including HSG silicon microstructures 28, 28a formed over the basic stud or cylinder configurations, thereby increasing the effective electrode surface area. Similarly, the bottom electrode 42 of FIG. 2 includes an HSG silicon layer 48 over the basic trench configuration, further increasing the electrode surface area.
In order to fully realize the advantage of the increased surface area of textured bottom electrodes, the capacitor dielectric layer should conform closely to the surface of the bottom electrode. While the dielectric thickness (xe2x80x9cdxe2x80x9d of the capacitance formula set forth above) should be minimized in order to maximize capacitance, too thin a capacitor dielectric risks leakage current across the capacitor electrodes. Leakage current may result from pinholes in the dielectric and quantum tunneling effects, both of which phenomena are more likely to occur with thinner dielectrics. Thin capacitor dielectric layers are thus characterized by a low breakdown voltage, limiting the charge that may be stored on the bottom electrode before breakdown leakage occurs. Accordingly, capacitor dielectric layers may be characterized by a certain minimal thickness necessary to avoid breakdown, depending upon the selected dielectric material.
Referring to FIG. 3, an enlarged view of an HSG silicon layer 50 is illustrated. The layer 50 comprises hemispherical grains 52 of conductively doped polycrystalline silicon (polysilicon, or simply poly) over a conductive substrate 54. The grains 52 have grain sizes ranging from about 50 xc3x85 to about 750 xc3x85. A dielectric layer 56, deposited by CVD, is shown over the HSG layer 50. The illustrated dielectric comprises conventional dielectric materials, such as silicon oxide (SiO2) and/or silicon nitride (Si3N4), which are well-understood and easily integrated with conventional fabrication process flows. CVD processes for these materials, for example, are well developed.
As shown, the dielectric layer 56 deposited by CVD is relatively conformal over the surfaces of the HSG silicon layer 50. However, conventional CVD processes cannot produce perfectly conformal dielectrics over high surface area textures, such as HSG silicon, due to a variety of factors. CVD inherently results in disparate deposition rates at different points of the topography across the workpiece. Non-uniformities in temperature across a workpiece, particularly across large workpieces like 300-mm wafers, can strongly influence thickness uniformity of a CVD layer. Variations in reactant concentration, due to reactor design, gas flow dynamics and the depletion effect, similarly affect the thickness uniformity across large workpieces. Due to these and other problems, growth rates and conformality cannot be controlled with absolute precision using conventional CVD.
Independently of variations across the workpiece, non-uniformity also results on a microlevel over rugged surfaces. In particular, at the neck region 60 between adjacent grains 52 that approach or intersect with one another, the dielectric layer bridges the adjacent grains 52 and produces an effectively greater dielectric thickness than over the top surfaces 61 of the grains. In some cases, reentrant profiles 62 are produced between blossoming or mushroom-shaped grains 52. CVD of a dielectric over the neck regions 60 of such structures results in either completely filling the neck region between grains 52 or leaving voids 64 between the grains 52 while the dielectric pinches off. In either case, the top electrode cannot conform to the surfaces of the grains 52, such that the lower portions of the grains 52 are effectively lost and do not contribute to capacitance.
If the dielectric 56 is deposited to the minimal thickness in neck regions 60 between HSG silicon grains, the dielectric over the top surfaces is too thin and can lead to leakage and consequent data errors. Accordingly, the dielectric 56 must be deposited to the minimal thickness required to avoid leakage over top surfaces 61 of the grains 52. The dielectric 56 at the neck regions 60 the grains 52 is thus thicker than theoretically necessary, leading to reduced capacitance. From another perspective, dielectric bridging across the neck regions 60 results in effective loss of surface area from lower portions of the HSG grains 52, such that the full advantage of HSG silicon is not realized.
Due in part to such limitations on capacitance enhancement by increasing electrode surface area, more recent attention has been focused instead upon methods of increasing the dielectric constant (k) of the capacitor dielectric. Much effort has been aimed at integrating new dielectric materials having higher k values. High k materials include aluminum oxide (Al2O3), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (ST), barium titanate (BT), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). These materials are characterized by effective dielectric constants significantly higher than conventional dielectrics (e.g., silicon oxides and nitrides). Whereas k equals 3.9 for silicon dioxide, the dielectric constants of these new materials can range from on the order of 10 (aluminum oxide) to 300 (BST), and some even higher (600 to 800). Using such materials enables much greater increases in cell capacitance/footprint.
Moreover, dramatic increases in k value for the capacitor dielectric allow use of smaller and simpler capacitor designs for a given stored charge requirement. Reducing the surface area needs for a cell capacitor can simplify the integration process and allow greater packing densities for future circuit designs.
Integrating high k materials into conventional process flows, however, has proven challenging. Some materials, such as Ta2O5, BST and other xe2x80x9cexoticxe2x80x9d materials, tend to involve highly oxidizing, high temperature deposition and post-deposition anneal conditions, leading to oxidation of traditional electrode materials and even diffusion of oxygen into lower circuit elements. Other materials, such as ZrO2 and TiO2, have highly inconsistent properties, depending upon a variety of processing conditions.
Accordingly, a need exists for more effective methods of increasing the storage capacitance for integrated memory cells.
In satisfaction of this need, methods are provided herein for depositing dielectric and top electrode materials over textured bottom electrode surfaces. Advantageously, the methods attain high conformality, such that only the minimum required thickness of the lining layer need be formed on all surfaces. The methods enable deposition of high dielectric constant (high k) materials over hemispherical grain (HSG) silicon under conditions favorable to maintaining silicon electrodes.
In general, the methods comprise cycles of alternating reactant phases, wherein each phase has a self-limiting effect. Metal oxides and ternary materials having dielectric constants of greater than about 10 can be formed by alternately adsorbing self-terminated metal or silicon complex monolayers through ligand-exchange reactions. The ligands present on the adsorbed metal or silicon complex are then removed by presence of an oxygen-containing species, leaving OH groups and oxygen bridges for halide or organic monolayers. Examples are provided herein for simple binary metal oxides, ternary materials such as metal silicates and nanolaminates comprising alternating ultrathin dielectric layers of different compositions.
Advantageously, the methods enable forming uniformly thick dielectric layers over HSG silicon, desirably as thin as possible without inducing leakage current through the capacitor dielectric so formed. Moreover, the methods facilitate a combination of high k materials with high surface area, textured electrodes. Capacitance is thus maximized, facilitating further scaling of critical dimensions without loss of cell reliability.
Similar alternating chemistries are preferably employed to form top electrode materials over the conformal dielectric layers. Examples are provided herein for metal nitride barriers as well as elemental metal layers. Following formation of thin, conformal conductive layer(s) by the preferred methods, conventional deposition with reduced conformality can complete the desired thickness of the top electrode without sacrificing capacitance. Conformal capacitor dielectric and top electrodes formed by the is preferred methods thus enable taking full advantage of the increased surface area afforded by textured bottom electrodes.